混合訊號 IC 電路設計(資深)工程師 / 主管(刊期已經結束)

1. Circuit design, IO circuit design 

2. 數位/類比電路設計

【本職缺僅接受台積電官方網站投遞】  

請至台積電官方網站投遞個人履歷表，此職缺履歷登錄網址: 

https://careers.tsmc.com/careers/JobDetail?jobId=343&source=1111 

Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. 

Responsibility: 

1. Design CMOS Image Sensor (CIS) & depth sensor related test chips for process development 

2. Design CIS or non-CIS test lines or test chips for process monitoring and improvement 

3. Data acquisition and analysis: CIS key performance indices and random noises characterization 

Diversity, Equity and Inclusion (DE&I) reflects TSMC’s core values and business philosophy and is essential for our future success. Our commitment to DE&I allows us to create an environment where every employee, regardless of gender, age, disability, religion, race, ethnicity, nationality, political affiliation, or sexual orientation, can bring their unique perspective and experiences to work, enabling us to drive profitability, increase productivity, and unleash innovation. To strive to create a workplace that is equitable and accessible to all employees, we also provide reasonable accommodations for qualified individuals with disabilities. We are committed to fostering an inclusive culture where every employee feels valued and empowered to contribute to our mission and provide excellent service to our global customers.

1. FPGA加速應用系統整合開發與驗證 

2. IP開發/驗證/整合 

3. 產品除錯與分析支援

振生半導體股份有限公司 (Jmem tek) 專注於半導體相關矽智財，提供設計服務與硬體資安專利，保護硬體資訊安全。如果您希望參與一個充滿潛力和創造力的環境，歡迎您加入我們的團隊。 

工作內容： 

• 混合訊號處理 (ADC, DAC, PLL) 

• 設計與開發PMIC相關電路 (Charge pump, LDO...) 

• 開發High power domain 電路與 core voltage domain 電路整合 

• 晶片整合並完成晶片驗證與T/O 

我們期望您具備的條件： 

• 碩士畢業，也歡迎新人。 

•有power相關電路開發經驗者。 

• 有Security IP (Ex: PUF, TRNG) 開發經驗者佳。 

相關報導： 

量子電腦資安攻防戰！振生半導體首創PUF+PQC市場唯一最佳解方https://udn.com/news/story/7240/7917935 

EE TIMES 報導：振生半導體引領IC安全創新 

https://www.eettaiwan.com/videos/jmem-technology-leads-ic-security-innovation/ 

2024台灣新創世界杯「振生半導體奪冠」　10月赴美爭百萬美元投資款 

https://finance.ettoday.net/news/2786606

應徵條件： 

1. 瑞昱強力招募(1)114年度研發替代役及(2)預聘114年應屆畢業之碩士、博士生。 

2. 碩士以上之電子、電機、電信、電控、資工等相關科系，並具下列任一條件者佳： 

a. 熟C、C++、Assembly、Linux、SPICE、Matlab、Cadence EDA環境。 

b. 熟類比電路設計、數位信號處理及有興趣者。 

c. 具ADC、PLL相關經驗及有興趣者。 

d. 對通訊網路、聯網多媒體、多媒體、電腦週邊、智慧互聯產品或程式設計有濃厚興趣者。

研究所以上電子、電機相關所組畢，具類比積體電路基礎 

工作內容： 

1. 類比積體電路設計 

2. 混合式積體電路設計

1.科系：碩士以上，理工相關系所(電子/電機系所,資訊工程所畢業尤佳)。 

2.班制：常日班。 

3.工作內容： 

(1)Responsible for SRAM Macro / SRAM Compiler Design. 

(2)SRAM Circuit Development; Verification and Maintenance 

4.說明： 

(1)請於履歷表中註明論文主題(方向)及所學專長。 

(2)請檢附學士(含)以上之成績單。

1.類比IC電路設計、模擬。 

2.與IC佈局工程師合作，完成佈局。 

3.有DC-DC converter、LDO、高壓製程經驗尤佳。

DRAM數位邏輯電路設計 

『具工作經驗者，薪資另議』

職務說明： 

1. Knowledge of micro-electronic engineering such as MOS I-V curve, op-amp operation point definition, semiconductor physics 

2. Knowledge of audio application such as amplifier, DAC, ADC, etc. 

3. Green hand of graduate school student who is major in electronic engineering is welcome

1. 類比IC設計 

2. 電源管理IC或ADC/PLL/Serdes類比電路整合及下線

Job Responsibilities 

• Work closely with circuit designers to complete the physical layout and its verification across different country. 

‒ Receive a schematic from an Analog IC Designer and use a CAD tool to graphically design the layers of that schematic. 

‒ Use problem solving & strong communication skills, , experience, and creativity to layout circuits that meet size, schedule, and performance specifications. 

• Run physical design verification tools to debug, improve, and verify layout blocks. 

Job Requirement 

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields with 3~5 years layout experience.  

‒ Including at 1~2 years in FINFET process node. 5nm/3nm is preferable. 

• Or 5+ years experience in IC layout design, especially ≥2 years in FINFET process node. 5nm/3nm is preferable. 

• Full-custom circuit layout/verification. Experience in one or more of the following area is preferable. 

‒ Mixed signal/analog/high speed layout, e.g. SerDes, ADC/DAC, PLL, etc. 

• Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS, etc). 

‒ Proficient at debugging/fixing LVS/DRC errors. 

• Experience with EMIR analysis, ESD, antenna and related layout solutions. 

• Must have strong communication skills and be a team player. 

• Ability to work independently & Collaborate with team members on continuous improvement opportunities in the flow, layout techniques, and design methodologies. 

• Each project can last from a couple months to a year and a half. 

• You will likely work on just one project in that time, but may be asked to switch to something else if priorities change. Your flexibility is appreciated. 

• Fluent in English is a plus.

職責要求 

1. Analog Circuit Design 

2. PLL/DLL、ADC/DAC、DC-DC Converter、LDO、Charge Pump IPs, etc 

任職資格 

1. 具備OPAmp or SAR ADC or PLL or PMIC電路設計者佳 

2. 具備量產的實際經驗者佳 

3. 熟悉Cadence/Synopsys EDA tool 

4. 歡迎積極主動、具備責任感、喜愛創新及團隊合作的人才加入 

5. 學歷 : 大學以上